LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;

ENTITY bit_shift4to5 IS
	PORT (
		--THESE PORTS SHOULD BE PORTMAPPED TO PHYSICAL PINS
		bits_in			: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
		
		--
		bits_out		: OUT STD_LOGIC_VECTOR(4 DOWNTO 0) := "00000";
		bits_out_P16	: OUT STD_LOGIC_VECTOR(4 DOWNTO 0) := "00000"
	);
END bit_shift4to5;

ARCHITECTURE Structure OF bit_shift4to5 IS
BEGIN
	bits_out <= '0' & bits_in;
	bits_out_P16 <= CONV_STD_LOGIC_VECTOR((UNSIGNED('0' & bits_in) + 16), 5);
END Structure;